1. Field of the Invention
This invention relates to semiconductor structures for integrated circuits (IC), and more particularly, to a stacked semiconductor structure for an IC device having a large number of junction devices, such as junction diodes, well resistors, N.sup.+ resistors, and bipolar junction transistors (BJT), which can help reduce the bulk of these junction devices in the IC device for high integration.
2. Description of Related Art
In the design and fabrication of an IC device having a large number of junction devices, such as diodes, well resistors, N.sup.+ resistors, and bipolar junction transistors (BJT), these junction devices typically require quite a large layout area on the wafer to realize. Therefore, the integration of the IC device is low.
Moreover, if these junction devices are to be formed in conjunction with a plurality of MOS (metal-oxide semiconductor) transistors on the same wafer, proper isolations have to be provided between these junction devices and the MOS transistors, or the undesired latch-up effect would occur and the operating voltage would be difficult to be controlled to the precise level.